I'm trying to use the DT022CTFT RGB interface with VSYNC, HSYNC, DOTCLK, and ENABLE. I'm looking at the following datasheet for reference (page 45 to 49):
Ilitek ILI9341 TFT Driver Datasheet
The timing diagram on page 49 is a little confusing as ENABLE appears high for several HSYNC cycles, but the diagram below shows it also oscillates.
Additionally, I am unclear as to how some of the parameters on page 46 fit into the previously mentioned timing diagram, like HBP, HAdr, etc.
Can I get any clarity on this or a more clear timing diagram?
Hi @Tom,
The timing diagrams you're referring to are a bit misleading/not shown to scale.
The purpose of the second diagram you mention is to demonstrate that the Data Enable signal is used to indicate when there is valid RGB data on the bus. So it is not that it oscillates, but is only meant to show that the RGB data is considered valid as long as the enable signal is high. Anything on the RGB bus when the enable signal is low, is simply ignored.
When a new frame of data is available, the following happens:
1. VSYNC signal goes low (and is read on the rising edge of DCLK) indicating a new frame.
2. HSYNC signal then goes low (and is read on the rising edge of DCLK), indicating that a new horizontal line is available.
3. VSYNC signal returns to a high state. The period of time that it was low (the VSYNC pulse) is referred to here as VLW.
3. The (high) DE signal is then used to indicate valid RGB data on the bus.
The time from the end of the VSYNC pulse (3) to the beginning of valid data (4) is referred to as the Vertical Back Porch. Likewise, the period from the last valid pixel data to the next VSYNC pulse is referred to as the Vertical Front Porch.
H-Addr & V-Addr are misprints. They should be H-Active & V-Active, which simply refer to the active frame width & height (in other words, the display resolution, 240 x 320).
We very much appreciate your patience and hope this answer helps you move forward!